(a) Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a method for manufacturing a semiconductor device having a damascene structure.
(b) Description of the Related Art
Recently, as semiconductor devices have become highly integrated and process technology has been enhanced, conventional aluminum wiring has been replaced by copper wiring for improving device characteristics such as operation speed and resistance of the device as well as parasitic capacitance between the metals. However, since copper has very poor etching characteristics, a damascene process is widely used for such a copper line instead of a conventional etching process.
In the damascene process, a dual damascene pattern including a via hole and a trench is formed in an interlayer insulating layer, and then copper is filled in the dual damascene pattern to form the copper metal line. The interlayer insulating layer is formed from undoped silicate glass (USG), a fluorine doped silicate glass (FSG), silicon nitride (SiN), etc. In some cases, a desired critical dimension (CD) may not be obtained when an upper profile of the trench is deformed. Such deformation may be due to an etch selectivity difference between the FSG and SiN layers.
In order to solve such a problem, a P—SiH4 layer (e.g., a plasma-deposited silicon oxide layer and/or a silicon oxide layer formed by plasma-enhanced deposition from a silane precursor gas, also known as PEOX) may be used instead of the SiN layer. In this case, the deformation of the upper profile of the trench may be prevented since the etch selectivity difference between the FSG layer and the P—SiH4 layer is not substantial. However, when an etching gas for FSG is used for etching the interlayer insulating layer having the P—SiH4 layer therein, etching of the interlayer insulating layer becomes locally poor, and thus the via hole and the trench may not be uniform.
Thus, according to a conventional method, via holes and trenches may not be uniformly fabricated. In such cases, metal lines may show different resistances thereby producing an undesirable effect on operation of the semiconductor device (e.g., different metal lines may exhibit different signal transmission speeds; in extreme cases, the difference may be sufficiently great that the device cannot with manufactured within predefined specifications, or acceptable parameter variation or tolerance ranges).
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form prior art that may be already known in this or any other country to a person of ordinary skill in the art.